1. Field of the Invention
The present invention relates to a semiconductor device which is almost free from what is called a surface step and can be fabricated with high packing density. The invention also pertains to a manufacturing process of such a semiconductor device.
2. Description of the Prior Art
Semiconductor devices have made remarkable progress in technologies for high packing density, high operating speed and low power. For higher packing density, techniques for field isolation, planarization of film surfaces and a multilevel metallization structure must be improved.
In the aspect of microfabrication technology, the definition of a submicron resist pattern has now been made possible with rapid progress in lithographic techniques such as electron beam lithography and X-ray lithography and, due to expeditious progress in dry etching techniques, submicron patterning, too, is becoming a reality. In contrast to such rapid advancement in the techniques for reducing the dimensions in the direction parallel to the specimen surface, the thicknesses of insulating and conducting films for multilevel interconnection in the direction perpendicular to the specimen surface cannot appreciably be reduced for such reasons as follows: (1) From the viewpoint of the electrical characteristics of devices, in order to make the most of improved device performances resulting from a reduction in size in the direction of the specimen surface, a wiring resistance cannot be increased; therefore, the film thickness cannot be decreased. (2) A decrease in the thickness of the insulating or conducting film may sometimes cause an increase in the influence of variation of the film thickness on the wiring resistance, or allow an increase in the number of pin holes, thereby to change the characteristics of the film, resulting in degraded film quality. For these reasons, as LSI becomes higher in packing density with an increase in the number of wiring layers, the height of the so-called surface step tends to increase relative to the dimensions in the direction parallel to the specimen relative surface. The surface step increase introduces poor step coverage of an overlying thin film and the possibilities of shorting and breakage of conducting interconnection lines. Moreover, since lithography is essentially susceptible to the influence of unevenness of the specimen surface, the finished dimensions of a pattern differ according to location on the specimen surface. That is to say, the resist film thickness is large on a depressed portion of the specimen surface and small on its projecting portion; therefore, even if exposed under the same exposure condition over the entire area of its surface, the resist film is developed to varying degrees, resulting in the pattern size on the depressed portion becoming smaller than that on the projecting portion.
A conventional solution to such problems is to increase the thckiness of the film covering the surface step or the resist film. When using a dry etching technique, the ratio in etching rate between the resist film and a film to be etched cannot be set large, so that when the film to be etched is thick, the resist film thickness must also be large enough to function as an etching mask. This, however, developes the defect that minimum film pattern dimensions which are obtainable inevitably become large, because the increased resist film thickness lowers resolution of the resist pattern by lithography. When using a wet etching process, the film being etched is subject to side etching; therefore, if its thickness is large, then its minimum pattern dimensions also increase.
The above indicates that the effect of high packing density is not so much heightened in proportion to an increase in the number of wiring layers for the multilevel interconnection. With a method that merely repeats the process of forming signal layer conductor networks several times, the number of conductive interconnection layers obtainable is only three to four at most.
To overcome the problems discussed above, planarization of each conductive interconnection layer has also been attempted in the past, too. The conventional planarization techniques are, for instance, an aluminum anodic process, a lift-off process and a resin coating process, but none of them is generally employed for the reasons to be given later. The aluminum anodic process is one that planarizes the layer surface by depositing aluminum all over the surface of an underlying layer or film. The aluminum at an area unnecessary for wiring is then converted into aluminum oxide (Al.sub.2 O.sub.3) through anodization. This process allows multilayer construction and prevents electro-migration, but it is defective in that the packing density is limited because the metallization pattern of the aluminum film has to be designed, in consideration of the anodization.
The lift-off technique is applied to a method of forming conductor networks first and then filling up the space between adjacent conductors with an insulator, or a method of depositing an insulating material in a predetermined pattern first and then forming the conductor networks. In either case, the film quality of the material to be recessed and easiness of the lift-off process are important. In order to carry out the lift-off process with ease, it is necessary that the material to be recessed be deposited, while maintaining the substrate temperature below 100.degree. to 150.degree. C. so as to suppress deposition of the material on the side surfaces of the substrate. The most favorable thin film deposition method in the prior art that meets such a requirement is an ion beam sputter deposition. But this method has such, short comings as follows: First, the density of the deposited film is low and poor in adhesion to the substrate and in acid resistance, and the pin hole density cannot be reduced. This is because the film composition is apt to deviate from its stoichiometric composition. To maintain the stoichiometric composition of the deposited film, a method that involves the addition of gas is generally employed. With this method, however, when adding gas during sputtering, the directionality of sputtered atoms and molecules is impaired to thereby increase the film thickness on the side wall of a surface step, making it impossible to carry out the lift-off process. Second, since the direction of dispersion of the sputtered atoms and molecules is continuously distributed, the side wall of the stepped portion is also deposited with a film of a thickness about one-half that of the film deposited on the flat surface portion. The film deposited on the side wall remains as a burr after the lift-off process. When removing the burr by etching, a groove may sometimes be made at a boundary of the remaining pattern.
Especially for silicon system materials which are important for fabrication of semiconductor integrated circuits, such as silicon nitride (Si.sub.3 N.sub.4), silicon oxide (SiO.sub.2), silicon (Si) and so forth, the ion beam sputter deposition technique has the drawback that high reliability patterning cannot be achieved through utilization of the lift-off technique. In other words, there has been no satisfactory lift-off technique of the abovesaid material because of the absence of a deposition technique capable of producing the high quality film.
With the resin coating technique, satisfactory planarity is unobtainable since the resin film thickness varies with the unevenness of the underlying layer. Accordingly, this method encounters such a problem that the condition of forming a through hole and the coverage of a film deposited upon the resin film differ according to location.
In an MOS LSI, a gate electrode is formed by a heat-resisting conductive layer, e.g. of polysilicon, refractory metal or refractory metal silicide, and source and drain diffusion layers are formed by the self alignment process using a heat-resisting conductive layer as a mask. In a miniaturized MOS LSI, however, although its dimensions are reduced in the direction parallel to the substrate surface, the thickness of the gate electrode cannot be reduced for the reason to be given below in addition to the same reasons as those referred to previously in respect to the interconnection layer.
That is to say, ion implantation is indispensable as an impurity introducing technique suitable for use with miniaturized devices. This is equally true in the case where a minimum pattern width of an LSI is in the submicron range. The gate electrode of the MOS LSI connot be reduced in thickness because it must be sufficiently thick to serve as a mask for ion implantation.
To settle the problems discussed above, it is very important to planarize the gate electrode of the MOS LSI. To this end, a selective oxidation technique for polysilicon and phosphorus-silicate glass flow techniques have heretofore been proposed, but neither of these is satisfactory for perfect planarization.
FIG. 1 illustrates, in cross section, a protion of a conventional MOS LSI. Reference numeral 1 indicates a p type silicon substrate; 2 designates a p type diffusion layer; 3 identifies a thick silicon dioxide film; 3' denotes a silicon dioxide film the thickness of which varies continuously; 4 represents a gate oxide film; 5 shows a gate electrode; 6 refers to an n.sup.+ diffusion layer; 7 and 9 signify conductors for wiring; and 8 indicates an insulating film. The thick silicon dioxide film 3 and the p type diffusion layer 2 are provided for electrically isolating transistors A and B from each other. This is a field isolation technology usually employed, and is called a selective oxidation technique since the thick silicon dioxide film 3 is formed by selective thermal oxidation of the surface of the silicon substrate 1 through using an oxidation resisting film as a mask.
This selective oxidation technique is advantageous in the following points: First, impurity introduction for forming the p type diffusion layer 2 and the formation of the thick silicon dioxide film 3 can be effected by one lithography process; second, a surface step is relatively small because the thick silicon dioxide film 3 is partly recessed into the silicon substrate 1.
However, the selective oxidation technique has such defects as follows:
First, there is a limit to miniaturization. The reason is that when forming the thick silicon dioxide film 3, the region 3' of continuously varying thickness (which is called a bird's beak after its cross-sectional configuration) is inevitably formed as shown in FIG. 2, and that the width of the bird's beak 3' (indicated by l.sub.1 in FIG. 2) is substantially equal to the thickness of the thick silicon dioxide film 3 (indicated by t.sub.1 in FIG. 2) and is limited in reduction. When the thick silicon dioxide film 3 is formed to a thickness of 1 .mu.m, the bird's beak 3' is also about 1 .mu.m wide; therefore, the region of the bird's beak 3' having a total of a 2 .mu.m or so width hinders the effective use of the active device area. At present, a minimum pattern dimension ranges from 1 to 3 .mu.m, and said value of approximately 2 .mu.m in the region of the bird's beak 3' is a serious obstacle to miniaturization. This problem will become more serious when the minimum pattern size is further reduced in future.
Second, long time thermal oxidation is required. For forming a 1 .mu.m thick selective oxide film, five to seven hours are needed in the case of a wet oxidation process which involves heat treatment at 1000.degree. C. This long time thermal oxidation is a problem in that it lowers productivity, grows a stacking fault in the silicon substrate and incurs inconvenient diffusion of the p type diffusion layer. An increase in the oxidation temperature for reducing the oxidation time would result in further growth of the stacking fault and further diffusion of the p type diffusion layer 2.
Third, satisfactory surface planarity cannot always be achieved. With a usual selective oxidation technique, since the oxide film is recessed to a depth about one-half the film thickness into the silicon substrate, a surface step height is about one-half the film thickness. For further reduction of this surface step height, there has been proposed such a method that entirely recesses the selective oxide film into the silicon substrate by forming the selective oxide film after partly etching away the surface of the silicon substrate With the use of this method, it is true that, as shown in FIG. 3, the surface of the selective oxide film (identified by C) and the surface of the silicon substrate surface (indicated by D) can be made level with each other, but a projection (which is called a bird's head after its configuration) 3" is inevitably formed at the peripheral portion of the selective oxide film in addition to the bird's beak 3'. Accordingly, this method cannot achieve satisfactory surface planarity, either.